OpenTestability

OpenTestability is an open-source structural analysis tool meticulously designed for digital circuits and their corresponding Verilog netlists. Its primary function is to compute critical testability metrics, such as SCOAP (Structural Controllability/Observability Program) and COP (Controllability/Observability Program) values. These metrics provide quantitative insights into the ease of setting a node to a specific logic value (controllability) and the ease of observing a node's value at a primary output (observability), which are fundamental for effective hardware engineering and testing.

This tool finds its application across a broad spectrum of scientific and engineering challenges within the integrated circuit design and electronic design automation (EDA) fields. It is instrumental in analyzing the testability of complex digital designs, identifying "hard-to-test" nodes, and guiding design-for-testability (DFT) efforts. Engineers and researchers can leverage OpenTestability to assess and improve the intrinsic testability of a circuit after various design optimizations, such as logic synthesis or restructuring, by quantifying the changes in SCOAP metrics for affected nodes.

Practical applications and use cases include:

• Design Verification and Testability Assessment​: Engineers can use OpenTestability to systematically define and compute controllability ($CC_0$, $CC_1$) and observability ($CO$) metrics for every node within a Verilog netlist, providing a comprehensive view of the circuit's inherent testability.
• Automatic Test Pattern Generation (ATPG): The tool's output metrics are crucial for guiding deterministic ATPG algorithms like the D-algorithm and PODEM. By providing objective selection heuristics that prioritize low controllability for fault excitation and low observability for fault propagation, OpenTestability helps to reduce the search depth and computational cost of generating test vectors.
• Hardware Security Analysis​: In the context of hardware Trojans, OpenTestability can identify circuit nodes with low controllability and observability. Such nodes are often exploited by malicious actors to create triggers that are difficult to activate or detect, making the tool vital for analyzing and bolstering circuit resilience against security threats.
• Benchmarking and Design Optimization​: The tool facilitates benchmarking and comparison of different circuit implementations or architectural choices based on their testability profiles, allowing for informed decisions that balance performance, area, and testability.