Clock Feedthrough

In the ideal world of circuit theory, a switch is a perfect device—it's either a seamless connection or a complete open. In the physical realm of microelectronics, however, this ideal breaks down. When a transistor acting as a switch turns off, it can leave behind a small but significant voltage error, a phenomenon known as clock feedthrough. This error poses a fundamental challenge to the design of high-performance analog and mixed-signal circuits, from data converters to audio systems. This article demystifies this critical effect, explaining its origins and consequences. The first chapter, "Principles and Mechanisms," will explore the underlying physics of capacitive coupling and charge injection that cause clock feedthrough. Subsequently, "Applications and Interdisciplinary Connections" will examine its real-world impact on circuit performance and discuss the ingenious design strategies, such as symmetric cancellation, that engineers employ to mitigate it.

Imagine you've built a tiny, perfect gate. Your job is simple: hold a bucket of water absolutely still. You open the gate, let the water level in the bucket match the reservoir outside, and then you slam the gate shut to trap the water. You expect the water level to stay put. But when you look, it's a little lower than you expected. A small splash seems to have leaped out, or perhaps the act of closing the gate itself somehow pushed some water away. In the world of microelectronics, engineers face this exact problem every billionth of a second. The "water" is electrical voltage, the "bucket" is a capacitor, and the "gate" is a transistor acting as a switch. The mysterious splash is an error we call ​​clock feedthrough​​, and understanding it is a delightful journey into the subtle physics of the very small.

Our first suspect in this microscopic mystery is a phenomenon as fundamental as static cling: capacitance. In an ideal world, the control signal that turns a transistor switch OFF (the "clock") would be perfectly isolated from the precious analog signal it's controlling. But on a silicon chip, "perfectly isolated" is a fantasy. The gate of a transistor—the terminal that receives the ON/OFF command—is a sliver of conductive material separated from the channel—the path for the signal—by an impossibly thin layer of insulator.

This structure, two conductors separated by an insulator, is the very definition of a ​​capacitor​​. So, even though there's no wire connecting the clock to the signal path, they are electrically coupled through these tiny, unavoidable "parasitic" capacitances. Think of the gate and the drain of a transistor as two small metal plates held very close to each other. They can't pass a steady current, but they can absolutely influence each other when voltages are changing.

Let's consider a simple sample-and-hold circuit with a single NMOS transistor switch. When it's time to hold the voltage, the clock signal applied to the gate plummets from a high voltage ($V_{high}$) to a low one ($V_{low}$). This sudden, negative-going voltage swing is capacitively coupled through the gate-to-drain overlap capacitance, which we can call $C_{GD,ov}$. It's as if the gate "pulls" on the charge stored on the hold capacitor, $C_H$.

The physics is beautifully simple. The hold capacitor and the parasitic capacitor form a ​​capacitive voltage divider​​. The change in gate voltage, $\Delta V_G = V_{low} - V_{high}$, gets divided between them. The resulting voltage error, $\Delta V_{out}$, on our hold capacitor is given by a simple ratio:

Since the gate voltage is dropping, $\Delta V_G$ is negative, and so is the error $\Delta V_{out}$. The held voltage is erroneously pulled down. The formula tells us a wonderful story. The error is worse if the parasitic coupling ($C_{GD,ov}$) is larger, or if the clock makes a bigger voltage swing ($\Delta V_G$). But we can fight back! By making our holding capacitor $C_H$ much larger than the parasitic one, we can make the error vanishingly small.

This isn't just a theoretical curiosity. In a typical high-precision circuit, this error can be substantial. For a D-MOSFET switch with a hold capacitor of $2.0 \text{ pF}$ and a gate-drain capacitance of just $15.0 \text{ fF}$ (a femtofarad is a millionth of a billionth of a farad!), a $-7.0 \text{ V}$ clock swing can induce an error of over $52 \text{ mV}$. In a world where we might be trying to measure signals with microvolt precision, this is a giant leap in the wrong direction.

Just as we think we've cornered our culprit, we find it has an accomplice. This second effect is more subtle and stems from the very nature of how a transistor works. When a MOSFET is ON, it's not just a passive wire. The gate voltage attracts a thin layer of mobile charge carriers (electrons in an NMOS) into the region just beneath it, forming a conductive "channel". You can picture this as a temporary river of charge, flowing and allowing current to pass.

What happens when we turn the switch OFF? The gate voltage changes, and the electric field holding this river in place collapses. The charge in the river—the ​​channel charge​​—has to go somewhere, and it gets expelled out both ends of the channel: back towards the input source and forward onto our holding capacitor. The portion that gets dumped onto the holding capacitor is a second source of error, known as ​​channel charge injection​​.

Let's dissect the error on a single NMOS switch, considering both mechanisms at once. The total voltage error, $\Delta V_{out}$, can be written in a way that lays the whole story bare:

Here, $Q_{inj}$ is the injected channel charge. Its amount depends on the size of the transistor (a wider, longer channel holds more charge) and how strongly the switch was turned ON. For an NMOS transistor, this charge is made of electrons, so $Q_{inj}$ is a negative quantity, which also tends to lower the held voltage. Now we see two distinct physical mechanisms, clock feedthrough and charge injection, adding together to corrupt our signal.

So, we have two villains working together. What can a clever engineer do? The answer is a stroke of genius, a beautiful example of using one problem to solve another. Instead of one switch, we'll use two: an NMOS transistor and a PMOS transistor, connected in parallel. This pair is called a ​​CMOS transmission gate​​.

The trick is how we drive them. The NMOS and PMOS are opposites. To turn the NMOS ON, its gate needs a high voltage; for the PMOS, its gate needs a low voltage. So, we drive their gates with complementary clock signals. When the NMOS gate goes from high to low to turn OFF, the PMOS gate goes from low to high.

Now, let's revisit clock feedthrough. The falling voltage on the NMOS gate couples a negative charge pulse onto our capacitor. But at the same time, the rising voltage on the PMOS gate couples a positive charge pulse! As derived in a foundational analysis, the total feedthrough voltage error is:

Look at that numerator: $(C_{gp} - C_{gn})$. Here, $C_{gn}$ and $C_{gp}$ are the effective coupling capacitances for the NMOS and PMOS transistors. If we can design our transistors such that their parasitic capacitances are equal ($C_{gp} = C_{gn}$), the two feedthrough effects cancel each other out perfectly. The positive kick from the PMOS exactly nullifies the negative pull from the NMOS. It's a perfect duel, orchestrated by design.

What about charge injection? The same magic can happen here. The NMOS channel is a river of negative electrons. The PMOS channel is a river of positive "holes". When the switch turns off, the NMOS dumps electrons (negative charge) onto the capacitor, while the PMOS dumps holes (positive charge). Again, we have opposing effects! By carefully sizing the transistors' widths and lengths, we can arrange for the injected negative charge from the NMOS to be cancelled by the injected positive charge from the PMOS.

This principle of cancellation is a cornerstone of high-performance analog design. We don't live in a perfect world free of parasitic effects. Instead, we learn the rules of the game and arrange for nature's imperfections to fight each other to a standstill.

Of course, the real world is always a bit messier than our elegant models. The cancellation in a CMOS switch, while powerful, is rarely perfect. The amount of channel charge in a transistor, for instance, depends not just on the gate voltage but also on the voltage of the signal being passed, $V_{in}$. This means that while we can achieve perfect charge injection cancellation at one specific input voltage, the cancellation will be imperfect for all others. The error becomes ​​signal-dependent​​, which can distort the signal in complex ways.

Furthermore, our analysis so far has assumed the clock switches instantaneously. In reality, it takes a finite time for the voltage to transition (it has a ​​slew rate​​). A slower clock transition gives the injected channel charge more time to leak away back to the low-impedance input, changing the final error value. A more advanced analysis shows that the error voltage depends on this slew rate, the transistor's ON-resistance, and the capacitor sizes in a more complex, dynamic interplay.

These second-order effects don't invalidate our core understanding, but they enrich it. They remind us that behind every simple model lies a deeper, more intricate reality. The journey from a simple, mysterious glitch to a deep understanding of parasitic coupling, charge injection, and elegant cancellation schemes reveals the heart of electronic design: a constant dance between unavoidable physics and human ingenuity.

Having peered into the microscopic origins of clock feedthrough, we might be tempted to dismiss it as a mere academic curiosity, a tiny puff of charge in the vast machinery of a modern microchip. But to do so would be a grave mistake. This seemingly innocuous effect is, in fact, a central character—often the villain—in the story of high-performance electronics. Its fingerprints are found everywhere, from the most sensitive scientific instruments to the device in your pocket. To the circuit designer, clock feedthrough is not a footnote; it is a formidable adversary to be outsmarted, a fundamental limitation to be overcome with cleverness and ingenuity. Let’s embark on a journey to see where this gremlin lurks and how engineers have learned to tame it.

At the heart of our digital world lies a crucial bridge: the interface between the smooth, continuous reality of analog signals and the crisp, discrete universe of ones and zeros. This is the domain of data converters, and it is here that clock feedthrough first makes its presence known in a most unwelcome way.

Consider the very first step in digitizing a signal: the sample-and-hold (S/H) circuit. Its job is simple in concept: at a precise moment, a switch closes, charging a capacitor to the input voltage, and then the switch opens, "holding" that voltage steady for the rest of the conversion process. But as we know, opening that MOS switch is not a clean break. As the control voltage on the gate plummets, it capacitively "pulls" on the holding capacitor through the device's parasitic capacitances. By the principle of charge conservation, this injected charge must create a voltage error. The voltage that is held is not the true input voltage, but a slightly corrupted version. For a single switch, this results in a small but definite voltage "glitch," a tiny error whose magnitude depends on the size of the clock swing and the ratio of the parasitic capacitance to the holding capacitance.

This initial error is just the beginning. In a complete Analog-to-Digital Converter (ADC), this tainted voltage is what the rest of the machine dutifully digitizes. The final digital number is, therefore, fundamentally flawed. What's worse, this error is often not even a simple, constant offset. The amount of charge injected can depend on the input signal level itself, a phenomenon tied to clock feedthrough's close cousin, charge injection. This means an ADC might be more inaccurate for quiet signals than for loud ones, introducing a subtle distortion. A 10-bit ADC, for example, might produce a digital code of 406 when it should have been 409, all because of these phantom charges injected at the moment of sampling.

The problem appears on the other side of the bridge as well. Imagine a high-fidelity Digital-to-Analog Converter (DAC) in a professional audio system. You send it a constant digital code, expecting a perfectly flat, silent DC voltage. Yet, if you were to look at the output with a sensitive spectrum analyzer, you might discover a faint, high-pitched hum—a spectral "spur" appearing precisely at the frequency of the DAC's internal master clock. Even with a static input, the chip's heart is still beating, and that clock signal is leaking, or "feeding through," into the analog output path, tainting the silence.

How do engineers fight back against such a fundamental and pervasive effect? One of the most elegant and powerful weapons in their arsenal is ​​symmetry​​. The idea is beautiful in its simplicity: if one switch injects an unwanted error, why not use a second, identical switch to create an identical, but opposite, error that cancels the first one out?

This is the principle behind ​​fully differential circuits​​. Instead of processing a signal on a single wire relative to ground, the signal is represented as the difference between two wires, a positive path ($V_p$) and a negative path ($V_n$). Each path has its own sample-and-hold circuit, its own switches, and its own capacitors. When the switches turn off, clock feedthrough injects an error charge onto both paths. If the circuit were perfectly symmetrical, the injected charge $\Delta Q$ would be identical on both sides. The voltage on both paths would glitch by the same amount. Since the final signal is the difference between the two paths, this "common-mode" error is perfectly subtracted out!

Of course, in the real world, nothing is perfect. Microscopic variations during chip fabrication mean that the capacitors might have a slight mismatch, $C_{H1} \ne C_{H2}$, or the transistors might inject slightly different amounts of charge, $\Delta Q_p \ne \Delta Q_n$. Because of this asymmetry, the cancellation is not perfect. A small portion of the common-mode error "leaks" through and becomes a differential error voltage. This highlights a profound concept in engineering: a differential architecture doesn't eliminate the error, but it converts the large, problematic error into a much smaller one that depends on the quality of the component matching. This technique is the bedrock of virtually all modern high-performance switched-capacitor filters and data converters, turning a show-stopping problem into a manageable one.

Clock feedthrough and its related effects are more insidious than just creating simple offsets. Because the amount of injected charge can depend nonlinearly on the signal voltage itself, the switch starts to behave like a component that introduces distortion.

Imagine feeding two pure musical tones, say at frequencies $\omega_1$ and $\omega_2$, into such a system. An ideal, linear system would output just those two tones. However, a system with signal-dependent clock feedthrough, modeled by an error term like $\Delta Q_{err} = k_2 V_{in}^2$, will mix them. The output will contain not only the original tones but also new, unwanted tones at frequencies like $\omega_1 + \omega_2$ and $\omega_1 - \omega_2$. This is known as ​​intermodulation distortion (IMD)​​, the bane of radio communications and high-fidelity audio. The clock feedthrough mechanism, by introducing a nonlinear charge transfer, becomes a source of IMD, corrupting the spectral purity of the signal.

Perhaps the most dramatic consequence of clock feedthrough is its connection to a catastrophic failure mode known as ​​latch-up​​. Deep within the silicon substrate of a CMOS chip, the layout of NMOS and PMOS transistors inadvertently creates a parasitic four-layer p-n-p-n structure, which is essentially a thyristor. Under normal operation, this parasitic device is off. However, if a sufficient transient current is injected into the chip's substrate, it can trigger this thyristor, creating a low-resistance path—a virtual short-circuit—between the power supply and ground. The resulting surge of current can permanently destroy the chip.

Where does this trigger current come from? You guessed it. Every time a MOS switch turns off, it injects a small packet of charge into the substrate via channel charge injection and gate-to-bulk clock feedthrough. A single injection is harmless. But a modern chip contains millions of switches, all turning on and off at gigahertz frequencies. The average substrate current is the charge per injection multiplied by the number of switches and the clock frequency. If this cumulative current becomes large enough, the voltage drop it creates across the substrate's own resistance can be sufficient to turn on the parasitic thyristor. Suddenly, there is a critical clock frequency, $f_{crit}$, above which the chip is at risk of self-destruction. What began as a tiny, femtocoulomb-level annoyance has become an existential threat to the entire system.

From corrupting data and creating distortion to threatening the very life of a chip, clock feedthrough is a powerful force. Understanding it is not just an exercise in physics; it is a vital part of the art of electronic design. It reminds us that in the quest for perfection, engineers are in a constant, clever battle against the fundamental, and sometimes feisty, laws of nature.