Stacked Transistors

In the landscape of electronic design, few principles are as simple yet powerful as the vertical stacking of transistors. This fundamental technique, akin to stacking building blocks, connects the output of one device to the input of another, unlocking new realms of performance. But how does this seemingly straightforward arrangement lead to the high-gain amplifiers, complex logic gates, and power-efficient processors that define modern technology? This article delves into the core of transistor stacking to answer that question. First, in "Principles and Mechanisms," we will dissect the physics behind the technique, exploring key configurations like the cascode, the incredible boost it provides to output resistance, and the inevitable price paid in voltage headroom. Then, in "Applications and Interdisciplinary Connections," we will see how these principles are ingeniously applied across the electronics landscape, from the pursuit of perfect analog signals to the challenges of digital logic and the physical realities of semiconductor fabrication.

Imagine you are building with LEGO bricks. You can place them side-by-side, or you can stack them one on top of the other. In the world of electronics, engineers discovered that stacking transistors—the fundamental building blocks of all modern circuits—unlocks remarkable new capabilities. This simple act of vertical arrangement, connecting the output of one transistor to the input of another, is a concept of profound elegance and utility, forming the backbone of everything from high-fidelity amplifiers to power-sipping microprocessors.

The idea of stacking transistors is as old as the integrated circuit itself. Early digital logic circuits, built from Bipolar Junction Transistors (BJTs), featured an output stage where the transistors were literally drawn one above the other in the schematic. This vertical arrangement of a pull-up transistor, a diode, and a pull-down transistor resembled the figures on a Native American totem pole, giving it the charming and enduring name ​​totem-pole output​​. This was perhaps the first inkling that there was something special about going vertical.

While the "totem-pole" was a push-pull driver, the most powerful and ubiquitous stacking technique in modern electronics, especially with Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), is the ​​cascode​​ configuration. Don't let the name intimidate you; it's just a specific recipe for stacking two transistors. You take a standard amplifying transistor (a "common-source" stage) and place a second transistor (a "common-gate" stage) directly on top of it. The bottom transistor does the main job of converting an input voltage signal into a current, while the top transistor's job is to act as a kind of steadfast shield. It takes the current from the bottom transistor and passes it along to the output, all while protecting the bottom transistor from the wild voltage swings happening at that output.

So, what's the magic? Why go to the trouble of adding this second "shield" transistor? The primary reason, and the one that revolutionised analog amplifier design, is the astonishing boost in ​​output resistance​​.

Think of it this way. The bottom transistor is like a worker trying to control the flow of water through a hose ($I_D$) by squeezing a handle (the input voltage $V_{GS}$). However, the person at the other end is erratically moving the output nozzle up and down (the fluctuating output voltage $V_{out}$). This chaotic movement makes it difficult for our worker to maintain a perfectly steady flow. The transistor's own finite output resistance, which we call $r_o$, is a measure of how much its current changes when the output voltage changes. For a perfect current source, this resistance would be infinite.

Now, we add the cascode transistor—a second worker. This new worker's only job is to hold the end of the first worker's hose at a fixed height, no matter what the person at the far end does. This top transistor uses its own control handle (its fixed gate bias) to absorb all the frantic up-and-down motion from the output. It presents a rock-steady voltage to the drain of the bottom transistor. Freed from the output chaos, the bottom transistor can now act like a much more perfect current source.

This "shielding" effect doesn't just add resistance; it multiplies it. A careful small-signal analysis reveals that the output resistance of the two-transistor stack isn't just $r_o + r_o$. Instead, it is approximately $g_m r_o^2$, where $g_m$ is the transconductance of the top transistor. Since the term $g_m r_o$ (the intrinsic voltage gain of a single transistor) is often a large number, like 50 or 100, the overall output resistance is magnified enormously. It's not uncommon for a cascode configuration to increase the output resistance by a factor of over 100!. This phenomenally high output resistance is the key ingredient for building amplifiers with extremely high voltage gain, a cornerstone of precision electronics.

As any physicist or engineer knows, there is no such thing as a free lunch. This incredible boost in performance comes at a price, and in the world of stacked transistors, that price is paid in ​​voltage headroom​​.

For a MOSFET to operate correctly as an amplifier, it must be in its "saturation" region. This requires the voltage drop across its drain and source terminals, $V_{DS}$, to be at least equal to its ​​overdrive voltage​​, $V_{ov}$. If the voltage drops below this, the transistor enters the "triode" region and stops behaving like a proper current source.

When you have a single transistor, the output voltage can swing down to just one overdrive voltage above ground ($V_{out,min} = V_{ov}$). But when you stack two transistors, both must remain in saturation. The bottom one needs $V_{ov}$, and the top one needs another $V_{ov}$ on top of that. This means the minimum possible output voltage is now the sum of their overdrive voltages ($V_{out,min} = V_{ov1} + V_{ov2}$).

A practical calculation vividly illustrates this trade-off: in a typical design, stacking two transistors might boost the output resistance from $250 \, \text{k}\Omega$ to an immense $63,000 \, \text{k}\Omega$. The cost? The minimum allowable output voltage might increase from $0.2 \, \text{V}$ to $0.4 \, \text{V}$. In a circuit powered by $5 \, \text{V}$, this might be a small price to pay. But in a modern smartphone chip running on less than $1 \, \text{V}$, every millivolt of available voltage swing is precious. This fundamental trade-off between gain and headroom is a central challenge that circuit designers constantly navigate.

So far, we've seen stacking as a tool for analog amplification. But what about the digital world of ones and zeros, where transistors act as simple on/off switches? Here, stacking serves entirely different, yet equally critical, purposes.

The most basic role is to perform logic. A two-input ​​NAND gate​​, for instance, is built by stacking two NMOS transistors in series in its pull-down network. Only when both inputs are HIGH (on) can current flow through the stack to pull the output LOW. This is a simple and elegant way to build fundamental logic functions.

However, this digital stacking introduces a subtle nuisance known as the ​​body effect​​. In a standard CMOS process, all NMOS transistors are built on a common silicon substrate (the "body"), which is tied to ground. For the bottom transistor in a stack, its source is also at ground, so its source-to-body voltage ($V_{SB}$) is zero. But for the transistor stacked above it, its source sits at a small positive voltage when current flows. This creates a positive $V_{SB}$, which has the unfortunate effect of increasing that transistor's ​​threshold voltage​​ ($V_{th}$)—the gate voltage needed to turn it on. A higher threshold voltage means the transistor is harder to switch on, making the logic gate slower. It's a parasitic effect that designers must account for to ensure their circuits meet performance targets.

But the story of digital stacking has a heroic ending. In the quest to save power in modern devices, stacking has become a lifesaver. A huge problem in chips with billions of transistors is ​​subthreshold leakage​​—a tiny current that trickles through transistors even when they are switched "off". While the leak from one transistor is minuscule, multiplying it by billions drains your battery, even when your device is idle.

The solution? The ​​stack effect​​. If you replace a single "off" transistor with a stack of two "off" transistors, the leakage current is drastically reduced. Here's how this beautiful piece of circuit physics works: the tiny leakage from the top transistor creates a small positive voltage at the intermediate node between the two. This small voltage has two powerful consequences. First, for the bottom transistor, its source is now slightly positive while its gate is at ground, creating a negative gate-to-source voltage. This pushes the transistor much deeper into its "off" state. Second, for the top transistor, the voltage drop across it is reduced, mitigating another leakage mechanism called Drain-Induced Barrier Lowering (DIBL).

The combined result, as detailed analysis shows, is an exponential reduction in leakage current. A simple stack of two can cut leakage by more than a factor of ten. It's a stunningly effective technique, turning the simple act of stacking into a powerful weapon against wasted energy and a key reason our mobile devices can last all day. From boosting gain to performing logic and, finally, to saving our batteries, the principle of stacking transistors remains one of the most versatile and ingenious tools in the engineer's toolkit.

Now that we have grappled with the inner workings of stacked transistors, we can take a step back and admire the view. Where does this seemingly simple trick of placing one transistor atop another actually take us? As with so many profound ideas in science and engineering, its consequences are far-reaching, weaving a thread that connects the delicate world of high-precision analog amplifiers, the lightning-fast logic of digital computers, and even the invisible dance of radio waves. It is a beautiful example of a single concept providing a key to unlock performance in a vast range of applications. This journey is a story of seeking perfection, paying the price, and then finding ingenious ways to cheat the bill.

In the analog domain, much of the game is a quest for control and stability. Imagine trying to build a perfectly steady source of current—a device that delivers the exact same amount of current regardless of the voltage tantrums thrown by the rest of the circuit. A single transistor is a decent, but flawed, current source. Its current output wavers slightly as the voltage across it changes. This imperfection is quantified by its finite output resistance, $r_o$. How can we do better?

The answer is to stack them. In a so-called ​​cascode​​ configuration, we place a second transistor on top of the first. The bottom transistor is still in charge of setting the current, but the top transistor acts as a shield. It absorbs the bulk of any voltage fluctuations from the output, dutifully passing along only a tiny, muffled version of that disturbance to the current-setting transistor below. The result is remarkable: the output resistance isn't just doubled; it's multiplied by the intrinsic gain of the shielding transistor, a factor of roughly $g_m r_o$. A simple current mirror with an output resistance of $r_o$ is transformed into a cascode mirror with an output resistance approaching $(g_m r_o) r_o$. We have created a current source that is hundreds or thousands of times more "stiff" and ideal, just by stacking two devices.

This trick is the secret ingredient for high-gain amplifiers. The voltage gain of a simple amplifier is its transconductance multiplied by its output resistance ($A_v = -g_m R_{out}$). To achieve immense gain, we need immense output resistance. An elegant way to do this is with the ​​telescopic cascode amplifier​​, which is essentially two cascode structures pitted against each other: an N-channel cascode pulling the output down and a P-channel cascode pulling it up. With both sides contributing enormous resistance, the total output resistance skyrockets, and so does the amplifier's gain. This is the brute-force application of stacking, a direct and powerful path to near-perfect amplification.

Alas, there is no free lunch in physics. The magnificent gain of a tall stack of transistors comes at a steep price: ​​voltage headroom​​. Think of the total supply voltage as the height of a room. Each transistor, to operate correctly in its active, high-resistance mode, requires a certain minimum voltage drop across it—its saturation voltage, $V_{ov}$. Each transistor in the stack "consumes" a slice of the total voltage height.

In a telescopic cascode, we might have a stack of four transistors between the positive and negative supply rails. If each requires, say, $0.15 \text{ V}$ to stay happy, the transistors themselves can consume $0.6 \text{ V}$ or more of the supply voltage, leaving very little room for the actual output signal to swing up and down before one of the transistors is forced out of its proper operating region. This is the central trade-off in much of analog design: the quest for high gain (by stacking) is in direct conflict with the need for a large output signal swing. In a world of ever-shrinking supply voltages for batteries and mobile devices, this "tyranny of headroom" is a primary challenge for circuit designers.

This is where the story gets truly clever. If stacking vertically causes problems, perhaps we can find another way. Engineers, faced with the headroom dilemma, developed beautiful and cunning topologies to get the benefits of cascoding without paying the full price.

One of the most important is the ​​folded cascode​​ architecture. Instead of stacking the input transistors directly underneath the cascode transistors, the signal path is "folded." The input transistors pull current downwards from a node, and this current is then mirrored and "folded" upwards into a separate cascode output stage. The genius of this arrangement is that the input and cascode transistors are no longer in the same direct vertical stack. This decouples their voltage requirements, dramatically increasing the range of input voltages the amplifier can handle and mitigating the headroom problem of the telescopic design. This elegant solution is a cornerstone of modern operational amplifiers and is even used in high-frequency circuits like the ​​Gilbert cell multiplier​​—a key component for mixing signals in radio transceivers—to enable their operation at the low supply voltages typical of mobile phones.

Another sophisticated escape is the ​​regulated cascode​​, or gain-boosted, topology. What if, instead of physically adding a third transistor to the stack to get even higher resistance, we could somehow simulate its effect? This is done using the power of feedback. A small auxiliary amplifier constantly monitors the voltage at the sensitive node between the two cascode transistors. If it detects any unwanted voltage variation, it immediately adjusts the gate of the top transistor to counteract it. This active regulation makes the top transistor behave as if it has a near-infinite resistance to disturbances, boosting the overall output impedance to astronomical levels—equivalent to a triple- or even quadruple-cascode, but without adding another device to the physical voltage stack. It is a sublime marriage of stacking and feedback, two of the most powerful concepts in electronics.

Shifting our focus from the continuous world of analog to the discrete 1s and 0s of digital logic, we find that the stacking principle is no less fundamental. Here, transistors are used as simple switches, but how they are stacked determines the logic they perform.

Consider a multi-input NAND gate, which implements the function NOT (A AND B AND C ... ). In the ubiquitous CMOS logic family, this is built with a stack of N-channel transistors in series, one for each input. For the output to be pulled to logic '0', all inputs must be '1', turning on every transistor in the stack to create a path to ground. The consequence? The resistance of all these switches in series adds up. For a gate with many inputs (a high "fan-in"), this stack can become quite resistive, like trying to drain water through a very long, thin straw. This makes the high-to-low transition of the output signal sluggish, limiting the gate's maximum operating speed.

This stack is also a point of vulnerability. If a manufacturing defect causes just one transistor in the series pull-down stack to be permanently "stuck-open," the entire path to ground is broken forever. If an input combination is applied where this broken path is supposed to be active, but the parallel pull-up network is also off, the output is connected to absolutely nothing. It floats in a ​​high-impedance state​​, neither a logic '0' nor a logic '1'. This undefined state can wreak havoc in a digital system, highlighting how critical the integrity of the stack is to basic logical function.

Stacking also enables complex logic in other, non-CMOS families. In the high-speed Emitter-Coupled Logic (ECL) family, transistors are stacked in a ​​series-gated​​ configuration. Here, the stack doesn't just act as a single switch but as a sophisticated tree that steers a constant current down one of several branches depending on the logic inputs. This allows for complex functions, like the sum output of a full adder ($S = A \oplus B \oplus C_{in}$), to be implemented elegantly and at very high speed within a single, multi-level current-steering stack.

Finally, our journey must return from abstract diagrams to the physical world of silicon. The beautiful architectures we can draw on paper are ultimately constrained by the messy realities of semiconductor fabrication. A striking example of this is found in the design of cascode circuits using bipolar junction transistors (BJTs).

In a standard bipolar integrated circuit process, designers have access to high-performance, vertically-structured NPN transistors whose collectors are electrically isolated. However, the process also yields vertical PNP transistors that have a critical structural limitation: their collectors are an inseparable part of the common silicon substrate, which must be tied to the most negative voltage in the circuit ($V_{EE}$).

This single fabrication detail has profound design consequences. It means you can easily build a high-performance NPN cascode current sink, because the output terminal—the collector of the cascode transistor—is a free node whose voltage can vary with the load. But you cannot build a high-performance cascode current source using the superior vertical PNPs, because its output terminal would be permanently hardwired to the negative supply rail, making it completely non-functional as a source. This physical asymmetry baked into the silicon forces the designer's hand, favoring NPN sink topologies over PNP source topologies. It is a powerful reminder that the art of circuit design is a conversation between theoretical ideals and physical possibility.

From building near-perfect amplifiers to crafting the fundamental gates of logic, the principle of stacking transistors is a unifying theme. It is a tool that provides immense power but demands a price, sparking a cycle of innovation and ingenuity that pushes the boundaries of electronic performance. It is a simple idea whose echoes are heard across the entire landscape of modern electronics.